High-speed PCBs and DDR5 Memory: Signal Integrity Discussions with Stephen Slater
As the world moves towards DDR5, a significant shift in design practices is underway. One of the key changes is the use of channel simulation tools for DDR5, marking a departure from traditional spice simulation methods. This transition is set to gather pace this year, with many more designs expected to emerge.
In this article, we delve into the intricacies of designing DDR5 PCBs, focusing on the critical issue of crosstalk reduction. Keysight Technologies, a global leader in electronic design automation software, provides valuable insights and solutions to help engineers navigate this challenging landscape.
Key Design Considerations for Reducing Crosstalk in DDR5 PCB Layouts
Keysight's High-Speed PCB Design Guide offers a comprehensive guide to designing DDR5 PCBs. The guide emphasises the importance of controlled impedance, trace spacing, grounding, and careful spacing/routing in reducing crosstalk.
- Controlled Impedance and Trace Spacing: Design trace widths and spacing according to copper thickness and the required impedance for DDR5 signals. Adequate spacing, such as ≥ 8 mil for 2 oz copper, is crucial to prevent crosstalk and flashover.
- Avoiding Stubbed or Unconnected Traces: Remove any stubs or unused branches in critical nets, especially differential pairs, to reduce reflections and resulting crosstalk.
- Continuous and Well-Managed Ground Planes: Keep ground planes continuous under critical memory traces like DDR5 signals. Split planes underneath these traces should be avoided to ensure a consistent return path that minimises loop areas and crosstalk.
- Ground Via Placement: Place ground vias around signal vias, especially near layer transitions, to maintain a close and low-inductance return current path, reducing electromagnetic interference and crosstalk.
- Routing Differential Pairs and Separation: Route differential pairs carefully, keeping transmit and receive pairs separated by at least five times the trace width (5W rule) if possible. If space is limited, maximise spacing and add ground fills between pairs or route pairs on opposite board sides separated by a ground plane.
- Minimising Stub Lengths on Vias: Keep stub lengths under about 15 mils for high-speed signals above 5 Gb/s to reduce reflections and crosstalk effects.
- Using Advanced Design and Simulation Tools: Employ simulation environments such as Keysight’s PathWave ADS Memory Designer for DDR5 to predict and optimise PCB designs to reduce jitter, reflection, and crosstalk before physical prototyping.
The Role of Simulation in High-Speed Board Design
Stephen Slater, a product manager in the High-Speed Digital Simulation Technology at Keysight, stresses the importance of simulating the whole system when designing high-speed boards, including the mainboard and connector, to ensure the design will work in various configurations.
Addressing Signal Integrity Issues in Pre-Layout Design
Signal integrity issues need to be considered in the pre-layout design of DDR5 due to the possibility of a completely closed eye at the input to the receiver. This is particularly important in high-speed serial links like 16 Gbps, where it is crucial to optimise the vias for signal integrity.
The Signal Integrity eBook by Keysight
Keysight's Signal Integrity eBook is a valuable resource for engineers, focusing on impedance discontinuities, crosstalk, reflections, ringing, overshoot and undershoot, and via stubs. The eBook is divided into 6 chapters and 53 pages, making it a 60-minute read.
Keysight's Advanced Design System: Pathwave ADS
Keysight's flagship product, Pathwave ADS, is an advanced design system with various tools for designing vias, schematic simulations, memory design, signal integrity, and power integrity. Pre-layout design is critical for DDR5 as it allows exploration of the design space to find out if there is enough design margin.
The Transition from DDR4 to DDR5
For those making the transition from DDR4 to DDR5, designs will need to be redesigned as it is a big technology change. Keysight's High-Speed PCB Design Guide consists of 8 chapters and 115 pages, providing a comprehensive resource for this transition.
In conclusion, the key approach to designing DDR5 PCBs is precise control of trace geometry, consistent ground referencing, minimising signal stubs, strategic via placement, and careful differential pair routing, combined with simulation-based validation to ensure DDR5 high-speed signals are clean and crosstalk is minimised. By following these guidelines, engineers can design robust and efficient DDR5 PCBs that meet the demands of today's high-speed digital world.
[1] Keysight Technologies. (2021). High-Speed PCB Design Guide. [Online]. Available: https://www.keysight.com/content/dam/keysight/en-us/assets/collateral/whitepapers/high-speed-pcb-design-guide.pdf [3] Keysight Technologies. (2021). High-Speed PCB Design Guide. [Online]. Available: https://www.keysight.com/content/dam/keysight/en-us/assets/collateral/whitepapers/high-speed-pcb-design-guide.pdf [5] Keysight Technologies. (2021). High-Speed PCB Design Guide. [Online]. Available: https://www.keysight.com/content/dam/keysight/en-us/assets/collateral/whitepapers/high-speed-pcb-design-guide.pdf
- The critical issue of crosstalk reduction in DDR5 PCB designs is addressed by Keysight Technologies through their High-Speed PCB Design Guide, which advocates for controlled impedance, trace spacing, grounding, and strategic routing to minimize crosstalk.
- In the shifting landscape of data-and-cloud-computing and technology, engineers can leverage technology, such as Keysight's PathWave ADS for DDR5, to predict and optimize PCB designs, addressing crosstalk and achieving clean high-speed signals.
